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RT8877C ? ds8877c-00 november 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dual-output pwm controller for amd svi2 cpu power supply applications z amd svi2 cpu z desktop computer general description the RT8877C is a 4 + 2 phases pwm controller. moreover, it is compliant with amd svi2 voltage regulator specification to support both cpu core (vdd) and northbridge portion of the cpu (vddnb). the RT8877C features ccrcot (constant current ripple constant on- time) with g-navp (green-native avp), which is a richtek's proprietary topology. g-navp makes it an easy setting controller to meet all amd avp (active voltage positioning) vdd/vddnb requirements. the droop is easily programmed by setting the dc gain of the error amplifier. with proper compensation, the load transient response can achieve optimized avp performance. the controller also uses the interface to issue votf complete and to send digitally encoded voltage and current values for the vdd and vddnb domains. it can operate in single phase and diode emulation mode and reach up to 90% efficiency in different modes according to different loading conditions. the RT8877C provides special purpose offset capabilities by pin setting. the RT8877C also provides power good indication, over current indication (ocp_l) and dual ocp mechanism for amd svi2 cpu core and nb. it also features complete fault protection functions including over voltage, under voltage and negative voltage. features z z z z z 4/3/2/1-phase (vdd) + 2/1/0-phase (vddnb) pwm controller z z z z z g-navp tm topology z z z z z support dynamic load line and zero load line z z z z z diode emulation mode at light load condition z z z z z svi2 interface to comply amd power management protocol z z z z z build-in adc for v out and i out reporting z z z z z immediate ov, uv and nv protections and uvlo z z z z z programmable dual ocp mechanism z z z z z 0.5% dac accuracy z z z z z fast transient response z z z z z power good indicator z z z z z over current indicator z z z z z 52-lead wqfn package z z z z z rohs compliant and halogen free v vddnb pwm4 RT8877C pwma1 ocp_l svd svt to cpu svc pwma2 rt9624a rt9624a rt9624a mosfet mosfet mosfet rt9624a mosfet rt9624a mosfet rt9624a mosfet v vdd pwm3 pwm2 pwm1 simplified application circuit
RT8877C 2 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin configurations wqfn-52l 6x6 (top view) pwm4 isen2n isen2p fb vsen isen4p isen4n isen3n isen3p isen1n isen1p tonset rgnd imon v064 imona vddio set1 svc svd svt ofs ofsa pgood isena1p en ibias compa fba vsena isena2p isena1n isena2n pgooda pwm2 pwm1 nc nc nc pwma2 dvd nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 25 24 23 22 21 20 19 18 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 41 42 43 44 45 46 47 48 49 50 51 52 vcc 28 ocp_l 27 set2 26 comp 13 tonseta 40 gnd 53 pwm3 pwma1 pwrok ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. package type qw : wqfn-52l 6x6 (w-type) RT8877C lead plating system z : eco (ecological element with halogen free and pb free) marking information RT8877Czqw : product number ymdnn : date code RT8877C zqw ymdnn
RT8877C 3 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1, 52, 51, 50 pwm4 to pwm1 pwm outputs for channel 1, 2, 3 and 4 of vdd controller. 2 tonset vdd controller on-time setting. connect this pin to the converter input voltage, vin, through a resistor, rton, to set the on-time of ugate and also the output voltage ripple of vdd controller. 5, 4, 8, 9 isen1n to isen4n negative current sense input of channel 1, 2, 3 and 4 for vdd controller. 6, 3, 7, 10 isen1p to isen4p positive current sense input of channel 1, 2, 3 and 4 for vdd controller. 11 vsen vdd controller voltage sense input. this pin is connected to the terminal of vdd controller output voltage. 12 fb output voltage feedback input of vdd controller. this pin is the negative input of the error amplifier for the vdd controller. 13 comp error amplifier output pin of the vdd controller. 14 rgnd return ground of vdd and vddnb controller. this pin is the common negative input of output voltage differential remote sense for vdd and vddnb controllers. 15 imon current monitor output for the vdd controller. this pin outputs a voltage proportional to the output current. 16 v064 fixed 0.64v reference voltage output. this voltage is only used to offset the output voltage of imon pin and imona pin. connect a 0.47 f capacitor from this pin to gnd. 17 imona current monitor output for the vddnb controller. this pin outputs a voltage proportional to the output current. 18 vddio processor memory interface power rail and serves as the reference for pwrok, svd, svc and svt. this pin is used by the vr to reference the svi pins. 19 pwrok system power good input. if pwrok is low, the svi interface is disabled and vr returns to boot-vid state with initial load line slope and initial offset. if pwrok is high, the svi interface is running and the dac decodes the received serial vid codes to determine the output voltage. 20 svc serial vid clock input from processor. 21 svd serial vid data input from processor. this pin is a serial data line. 22 svt serial vid telemetry input from vr. this pin is a push-pull output. 23 ofs over clocking offset setting for the vdd controller. 24 ofsa over clocking special purpose offset setting for the vddnb controller. 25 set1 ocp_tdc threshold setting individually for vdd and vddnb controllers and also the internal ramp slew rate setting (rset and rseta) individually for vdd and vddnb controllers 26 set2 quick response threshold setting individually for vdd and vddnb controllers (qrth and qrtha) and also the ocp_tdc trigger delay time setting for both controllers and over clocking offset enable setting. 27 ocp_l over current indicator for dual ocp mechanism. this pin is an open drain output. 28 vcc controller power supply input. connect this pin to 5v with an 1 f or greater ceramic capacitor for decoupling.
RT8877C 4 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no. pin name pin function 29 ibias internal bias current setting. connect only a 100k resistor from this pin to gnd to generate bias current for internal circuit. place this resistor as close to ibias pin as possible. 30 compa error amplifier output of the vddnb controller. 31 fba output voltage feedback input of vddnb controller. this pin is the negative input of the error amplifier for the vddnb controller. 32 vsena vddnb controller voltage sense input. this pin is connected to the terminal of vddnb controller output voltage. 33, 36 isena2p, isena1p positive current sense input of channel 1 and 2 for vddnb controller. 34, 35 isena2n, isena1n negative current sense input of channel 1 and 2 for vddnb controller. 37 en controller enable pin. a logic high signal enables the controller. 38 pgooda power good indicator for the vddnb controller. this pin is an open drain output. 39 pgood power good indicator for the vdd controller. this pin is an open drain output. 40 tonseta vddnb controller on-time setting. connect this pin to the converter input voltage, vin, through a resistor, rtonnb, to set the on-time of ugate_vddnb and also the output voltage ripple of vddnb controller. 41, 42 pw ma2, pw ma1 pwm output for channel 1 and 2 of vddnb controller. 43, 44, 45, 47, 48, 49 nc no internal connection. 46 dvd external driver power supply input voltage detection pin. 53 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
RT8877C 5 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram set2 fb comp rgnd pwm4 pwm3 pwm2 pwm1 isen4n fba compa pwma1 ton gena loop control protection logic mux svi2 interface configuration registers control logic tonseta rgnd soft-start & slew rate control vset uvlo ov/uv/nv ibias ofs/ofsa load line /load line a error amp from control logic offset cancellation isen4p isen3n isen3p isen2n isen2p isen1n isen1p current balance to protection logic + - + - dac + - soft-start & slew rate control vseta error amp from control logic offset cancellation + - dac pwm cmpa ton gen adc + - + - + - + - set1 ofs ofsa imoni imonai vsen vsena svc svd svt vddio pwrok en dvd vcc + - rset/rseta + qra tona pwma2 rseta current mirror ib1 current mirror ib2 current mirror ib3 current mirror ib4 + - ocp_tdc, ocp_spike oc vsen imon v064 pwm cmp + - current mirror + - current mirror isena1n isena1p isena2n isena2p imona + - ov/uv/nv to protection logic vsena oca ocp_tdca, ocp_spikea pgood pgooda ocp_l qr ton + - + rset tonset gnd current balance iba1 iba2 ib4 ib3 ib1 ib2 average imoni iba1 iba2 average imonai 0.4 v064 0.4 ocp threshold x1 x1 x1 x1 x2 x2
RT8877C 6 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation mux and adc the mux supports the inputs from set1, set2, ofs, ofsa, imon, imona, vsen, or vsena. the adc converts these analog signals to digital codes for reporting or performance adjustment. svi2 interface the svi2 interface uses svc, svd, and svt pins to communicate with cpu. RT8877C's performance and behavior can be adjusted by commands sent by cpu or platform. uvlo the uvlo detects dvd and vcc pin voltages for under voltage lockout protection and power on reset operation. loop control protection logic loop control protection logic detects en and uvlo signals to initiate soft-start function and control pgood, pgooda and ocp_l signals after soft-start is finished. when ocp event is triggered, the ocp_l pin voltage will be pulled low. dac the dac receives vid codes from the svi2 control logic to generate an internal reference voltage (vset/vseta) for controller. soft-start and slew-rate control this block controls the slew rate of the internal reference voltage when output voltage changes. error amp error amplifier generates comp/compa signal by the difference between vset/vseta and fb/fba. offset cancellation this block cancels the output offset voltage from voltage ripple and current ripple to achieve accurate output voltage. pwm cmpx the pwm comparator compares comp signal and current feedback signal to generate a signal for tongenx. tongen/tongena this block generates an on-time pulse which high interval is based on the on-time setting and current balance. current balance per-phase current is sensed and adjusted by adjusting on-time of each phase to achieve current balance for each phase. oc/ov/uv/nv vsen/vsena and output current are sensed for over current, over voltage, under voltage, and negative voltage protection. rset/rseta the ramp generator is designed to improve noise immunity and reduce jitter.
RT8877C 7 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. svid [7:0] voltage (v) svid [7:0] voltage (v) svid [7:0] voltage (v) svid [7:0] voltage (v) 0000_0000 1.55000 0010_0111 1.30625 0100_1110 1.06250 0111_0101 0.81875 0000_0001 1.54375 0010_1000 1.30000 0100 _1111 1.05625 0111_0110 0.81250 0000_0010 1.53750 0010_1001 1.29375 0101_0000 1.05000 0111_0111 0.80625 0000_0011 1.53125 0010_1010 1.28750 0101_0001 1.04375 0111_1000 0.80000 0000_0100 1.52500 0010_1011 1.28125 0101_0010 1.03750 0111_1001 0.79375 0000_0101 1.51875 0010_1100 1.27500 0101_0011 1.03125 0111_1010 0.78750 0000_0110 1.51250 0010_1101 1.26875 0101_0100 1.02500 0111_1011 0.78125 0000_ 0111 1.50625 0010_1110 1.26250 0101_0101 1.01875 0111_1100 0.77500 0000_1000 1.50000 0010_1111 1.25625 0101_0110 1.01250 0111_1101 0.76875 0000_1001 1.49375 0011_0000 1.25000 0101_0111 1.00625 0111_1110 0.76250 0000_1010 1.48750 0011_0001 1.24375 0101_1000 1.00000 0111_1111 0.75625 0000_1011 1.48125 0011_0010 1.23750 0101_1001 0.99375 1000_0000 0.75000 0000_1100 1.47500 0011_0011 1.23125 0101_1010 0.98750 1000_0001 0.74375 0000_1101 1.46875 0011_0100 1.22500 0101_1011 0.98125 1000_0010 0.73750 0000_1110 1.46250 0011_0101 1.21875 0101_1100 0.97500 1000_0011 0.73125 0000_1111 1.45625 0011_0110 1.21250 0101_1 101 0.96875 1000_0100 0.72500 0001_0000 1.45000 0011_0111 1.20625 0101_1110 0.96250 1000_0101 0.71875 0001_0001 1.44375 0011_1000 1.20000 0101 _1111 0.95625 1000_0110 0.71250 0001_0010 1.43750 0011_1001 1.19375 0110_0000 0.95000 1000_0111 0.70625 0001_0011 1.43125 0011_1010 1.18750 0110_0001 0.94375 1000_1000 0.70000 0001_0100 1.42500 0011_1011 1.18125 0110_0010 0.93750 1000_1001 0.69375 0001_0101 1.41875 0011_1100 1.17500 0110_0011 0.93125 1000_1010 0.68750 0001_0110 1.41250 0011_1101 1.16875 0110_0100 0.92500 1000_1011 0.68125 0001_ 0111 1.40625 0011_1110 1.16250 0110_0 101 0.91875 1000_1100 0.67500 0001_1000 1.40000 0011_1 111 1.15625 0110_0110 0.91250 1000_1101 0.66875 0001_1001 1.39375 0100_0000 1.15000 0110_0111 0.90625 1000_1110 0.66250 0001_1010 1.38750 0100_0001 1.14375 0110_1000 0.90000 1000 _1111 0.65625 0001_1011 1.38125 0100_0010 1.13750 0110_1001 0.89375 1001_0000 0.65000 0001_1100 1.37500 0100_0011 1.13125 0110_1010 0.88750 1001_0001 0.64375 0001_1101 1.36875 0100_0100 1.12500 0110_1011 0.88125 1001_0010 0.63750 0001_1110 1.36250 0100_0101 1.11875 0110_1100 0.87500 1001_0011 0.63125 0001_1111 1.35625 00 10_0110 1.11250 0110_1101 0.86875 1001_0100 0.62500 0010_0000 1.35000 0100_0111 1.10625 0110_1110 0.86250 1001_0101 0.61875 0010_0001 1.34375 0100_1000 1.10000 0110_1111 0.85625 1001_0110 0.61250 0010_0010 1.33750 0100_1001 1.09375 0111_0000 0.85000 1001_0111 0.60625 0010_0011 1.33125 0100_1010 1.08750 0111_0001 0.84375 1001_1000 0.60000 0010_0100 1.32500 0100_1011 1.08125 0111_0010 0.83750 1001_1001 0.59375 0010_0101 1.31875 0100_1100 1.07500 0111_0011 0.83125 1001_1010 0.58750 0010_0110 1.31250 0100_1101 1.06875 0111_0100 0.82500 1001_1011 0.58125 table 1. serial vid codes
RT8877C 8 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. svid [7:0] voltage (v) svid [7:0] voltage (v) svid [7:0] voltage (v) svid [7:0] voltage (v) 1001_1100 0.57500 1011_0101 * 0.41875 1100_1110 * 0.26250 1110_0111* 0.10625 1001_1101 0.56875 1011_0110 * 0.41250 1100_1111 * 0.25625 1110_1000* 0.10000 1001_1110 0.56250 1011_0111 * 0.40625 1101_0000 * 0.25000 1110_1001* 0.09375 1001_1111 0.55625 1011_1000 * 0.40000 1101_0001 * 0.24375 1110_1010* 0.08750 1010_0000 0.55000 1011_1001 * 0.39375 1101_0010 * 0.23750 1110_1011* 0.08125 1010_0001 0.54375 1011_1010 * 0.38750 1101_0011 * 0.23125 1110_1100* 0.07500 1010_0010 0.53750 1011_1011 * 0.38125 1101_0100 * 0.22500 1110_1101* 0.06875 1010_0011 0.53125 1011_1100 * 0.37500 1101_0101 * 0.21875 1110_1110* 0.06250 1010_0100 0.52500 1011_1101 * 0.36875 1101_0110 * 0.21250 1110_1 111* 0.05625 1010_0101 0.51875 1011_1110 * 0.36250 1101_0111 * 0.20625 1111_0000* 0.05000 1010_0110 0.51250 1011_1111 * 0.35625 1101_1000 * 0.20000 1111_0001* 0.04375 1010_0111 0.50625 1100_0000 * 0.35000 1101_1001 * 0.19375 1111_0010* 0.03750 1010_1000 * 0.50000 1100_0001 * 0.34375 1101_1010 * 0.18750 1111_0011* 0.03125 1010_1001 * 0.49375 1100_0010 * 0.33750 1101_1011 * 0.18125 1111_0100* 0.02500 1010_1010 * 0.48750 1100_0011 * 0.33125 1101_1100 * 0.17500 1111_0101* 0.01875 1010_1011 * 0.48125 1100_0100 * 0.32500 1101_1101 * 0.16875 1111_0110* 0.01250 1010_1100 * 0.47500 1100_0101 * 0.31875 1101_1110 * 0.16250 1111_0 111* 0.00625 1010_1101 * 0.46875 1100_0110 * 0.31250 1101_1111 * 0.15625 1111_1000* 0.00000 1010_1110 * 0.46250 1100_0111 * 0.30625 1110_0000* 0.15000 1111_1001* off 1010_1111 * 0.45625 1100_1000 * 0.30000 1110_0001* 0.14375 1111_1010* off 1011_0000 * 0.45000 1100_1001 * 0.29375 1110_0010* 0.13750 1111_1011* off 1011_0001 * 0.44375 1100_1010 * 0.28750 1110_0011* 0.13125 1111_1100* off 1011_0010 * 0.43750 1100_1011 * 0.28125 1110_0100* 0.12500 1111_1101* off 1011_0011 * 0.43125 1100_1100 * 0.27500 1110_0101* 0.11875 1111_1110* off 1011_0100 * 0.42500 1100_1101 * 0.26875 1110_0110* 0.11250 1111_1111* off * indicates tob is 80mv for this vid code; unconditional vr controller stability required at all vid codes
RT8877C 9 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 2. set1 pin setting for vdd controller set1 pin voltage before current injection v set1 (mv) ocp_tdc (respect to ocp_spike) rset set1 pin voltage before current injection v set1 (mv) ocp_tdc (respect to ocp_spike) rset 34 145% 836 145% 59 130% 861 130% 85 115% 886 115% 110 100% 911 100% 135 85% 936 85% 160 45% 70% 961 65% 70% 235 145% 1036 145% 260 130% 1061 130% 285 115% 1086 115% 310 100% 1112 100% 335 85% 1137 85% 360 50% 70% 1162 70% 70% 435 145% 1237 145% 460 130% 1262 130% 485 115% 1287 115% 510 100% 1312 100% 535 85% 1337 85% 560 55% 70% 1362 75% 70% 636 145% 1437 145% 661 130% 1462 130% 686 115% 1487 115% 711 100% 1512 100% 736 85% 1537 85% 761 60% 70% 1562 disable 70%
RT8877C 10 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 3. set1 pin setting for vddnb controller set1 pin voltage difference v set1 (before and after current injection) (mv) ocp_tdca (respect to ocp_spikea) rseta set1 pin voltage difference v set1 (before and after current injection) (mv) ocp_tdca (respect to ocp_spikea) rseta 34 145% 836 145% 59 130% 861 130% 85 115% 886 115% 110 100% 911 100% 135 85% 936 85% 160 45% 70% 961 65% 70% 235 145% 1036 145% 260 130% 1061 130% 285 115% 1086 115% 310 100% 1112 100% 335 85% 1137 85% 360 50% 70% 1162 70% 70% 435 145% 1237 145% 460 130% 1262 130% 485 115% 1287 115% 510 100% 1312 100% 535 85% 1337 85% 560 55% 70% 1362 75% 70% 636 145% 1437 145% 661 130% 1462 130% 686 115% 1487 115% 711 100% 1512 100% 736 85% 1537 85% 761 60% 70% 1562 disable 70%
RT8877C 11 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 4. set2 pin setting set2 pin voltage before current injection v set2 (mv) qrth (for vdd) ocptrgdelay [1:0] ocptrgdel ay (for vdd/vddnb) 19 00 10ms 72 01 20ms 122 10 30ms 172 disable 11 4 0m s 222 00 10ms 272 01 20ms 323 10 30ms 373 35mv 11 4 0m s 423 00 10ms 473 01 20ms 523 10 30ms 573 39mv 11 4 0m s 623 00 10ms 673 01 20ms 723 10 30ms 773 43mv 11 4 0m s 823 00 10ms 874 01 20ms 924 10 30ms 974 47mv 11 4 0m s 1024 00 10ms 1074 01 20ms 1124 10 30ms 1174 51mv 11 4 0m s 1224 00 10ms 1274 01 20ms 1324 10 30ms 1375 55mv 11 4 0m s 1425 00 10ms 1475 01 20ms 1525 10 30ms 1575 60mv 11 4 0m s
RT8877C 12 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 5. quick response threshold for vddnb controller set2 pin voltage difference v set2 (before and after current injection) (mv) ofsenable ofsaenable qrth [2:0] qrtha (for vddnb) 19 000 disable 72 001 35mv 122 010 39mv 172 011 43mv 222 100 47mv 272 101 51mv 323 110 55mv 373 0 111 59mv 423 000 disable 473 001 35mv 523 010 39mv 573 011 43mv 623 100 47mv 673 101 51mv 723 110 55mv 773 0 1 111 59mv 823 000 disable 874 001 35mv 924 010 39mv 974 011 43mv 1024 100 47mv 1074 101 51mv 1124 110 55m v 1174 0 111 59mv 1224 000 disable 1274 001 35mv 1324 010 39mv 1375 011 43mv 1425 100 47mv 1475 101 51mv 1525 110 55mv 1575 1 1 111 59mv
RT8877C 13 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics parameter symbol test conditions min typ max unit input power supply supply current i vcc en = 3v, not switching -- -- 12 ma shutdown current i shdn en = 0v -- -- 5 a reference and dac v fb = 1.0000 ? 1.5500 (no load, ccm mode) ? 0.5 0 0.5 %svid v fb = 0.8000 ? 1.0000 ? 5 0 5 v fb = 0.3000 ? 0.8000 ? 8 0 8 dc accuracy v fb v fb = 0.2500 ? 0.3000 ? 80 0 80 mv rgnd current rgnd current i rgnd en = 3v, not switching -- -- 200 a slew rate dynamic vid slew rate sr setvid fast 7.5 12 -- mv/ s error amplifier input offset v eaofs -- -- 2 mv dc gain adc r l = 47k 70 80 -- db gain-bandwidth product gbw c load = 5pf -- 10 -- mhz output voltage range v comp 0.3 -- 3.6 v maximum source current iea, src 1 -- -- ma maximum sink current iea, snk 1 -- -- ma (v cc = 5v, t a = 25 c, unless otherwise specified) recommended operating conditions (note 4) z supply voltage, vcc ---------------------------------------------------------------------------------------------- 4.5v to 5.5v z junction temperature range ------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z vcc to gnd --------------------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z rgnd to gnd ------------------------------------------------------------------------------------------------------- ? 0.3v to 0.3v z tonset to gnd ---------------------------------------------------------------------------------------------------- ? 0.3v to 28v z other pins ------------------------------------------------------------------------------------------------------------ ? 0.3v to (v cc + 0.3v) z power dissipation, p d @ t a = 25 c wqfn-52l 6x6 ----------------------------------------------------------------------------------------------------- 3.77w z package thermal resistance (note 2) wqfn-52l 6x6, ja ------------------------------------------------------------------------------------------------ 26.5 c/w wqfn-52l 6x6, jc ----------------------------------------------------------------------------------------------- 6.5 c/w z junction temperature ---------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ---------------------------- -------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) --------------------------------------------------------------------------------------- 2kv
RT8877C 14 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit current sense amplifier input offset voltage v oscs ? 0.2 -- 0.2 mv current mirror gain for core a mirror, vdd 97 -- 103 % current mirror gain for nb a mirror, vddnb 194 -- 206 % impedance at negative input r isenxn 1 -- -- m impedance at positive input r isenxp 1 -- -- m internal sum current sense dc gain for core ai, vdd vdd controller -- 0.4 -- v/v internal sum current sense dc gain for nb ai, vddnb vddnb controller -- 0.8 -- v/v maximum source current ics, src 0 < v fb < 2.35 100 -- -- a maximum sink current ics, snk 0 < v fb < 2.35 12 -- -- a zero current detection zero current detection threshold v zcd_th v zcd_th = gnd ? v phasex -- 1 -- mv ton setting tonsetx pin minimum voltage v ton, min -- 0.5 -- v tonsetx ton t on i rton = 80 a, v fb = 1.1v 270 305 340 ns tonsetx input current range i rton v fb = 1.1v 25 -- 280 a minimum toff t off -- 250 -- ns ibias ibias pin voltage v ibias r ibias = 100k 1.97 2 2.03 v v064 reference voltage output v 064 0.61 0.64 0.67 v sink current capability i v064, snk v064 = 0.64v 800 -- -- a source current capability i v064, src -- -- 100 a board ofsx vfb limit v fb, limit 0 -- 2.35 v ofs update rate f ofs -- 50 -- khz board offset resolution v ofs -- 6.25 -- mv logic inputs logic-high v ih_en 2 -- -- en input voltage logic-low v il_en -- -- 0.8 v leakage current of en i lek_en ? 1 -- 1 a logic-high v ih_svi respect to vddio 70 -- 100 svc, svd, svt, pwrok logic-low v il_svi respect to vddio 0 -- 35 % hysteresis of svc, svd, svt, pwrok v hys_svi respect to vddio 10 -- -- %
RT8877C 15 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit protection under voltage lock out threshold v uvlo vcc falling edge 4 4.2 4.4 v under voltage lock out hysteresis v uvlo -- 100 -- mv under voltage lock out delay t uvlo v cc rising abov e u vlo threshold -- 3 -- s over voltage protection threshold v ovp 275 325 375 mv over voltage protection delay t ov p v sen rising above threshold -- 1 -- s under voltage protection threshold v uvp ? 375 ? 325 ? 275 mv under voltage protection delay t uvp v sen falling below threshold -- 3 -- s negative voltage protection threshold v nv -- 0 -- mv per phase ocp threshold i ocp_ perph ase i isenxn per-phase ocp threshold. -- 10 -- a delay of per phase ocp t phocp -- 1 -- s ocp_spike threshold i ocp_ spike dcr = 0.95m , r sense = 680 , r imon = 10k 162 180 198 a ocp_spike action delay t ocpspike _action_dly 6 -- 12 s ocp_tdc action delay t ocptdc _action_dly 12 -- 24 s ocp_l, pgood and pgooda output low voltage at ocp_l v ocp_l i ocp_l = 4ma 0 -- 0.2 v ocp_l assertion time t ocp_l 2 -- -- s output low voltage at pgood, pgooda v pgood , v pgooda , i pgood = 4ma, i pgooda = 4ma 0 -- 0.2 v pgood and pgooda threshold voltage v th_pgood v th_pgooda respect to v boot -- ? 300 -- mv pgood and pgooda delay time t pgood t pgooda v sen = v boot to pgood/pgooda high 70 100 130 s current report maximum reported current (ffh = ocp) -- 100 -- %idd_sp ike_ocp minimum reported current (00h) -- 0 -- %idd_sp ike_ocp iddspike current accuracy -- -- 3 %
RT8877C 16 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit voltage report maximum reported voltage (0_00h) -- 3.15 -- v minimum reported voltage (1_f8h) -- 0 -- v voltage accuracy ? 2 -- 2 lsb qr setting of vdd and vddnb quick response threshold voltage setting range minimum value v qrth, minx qrthx [2:0] = [001] -- 35 -- mv quick response threshold voltage setting range maximum value v qrth, maxx qrthx [2:0] = [111] -- 60 -- mv pwm driving capability pwmx source resistance r pwm_src -- 20 -- pwmx sink resistance r pwm_snk -- 10 --
RT8877C 17 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit tonseta RT8877C set2 26 40 2 tonset 25 24 23 set1 ofsa ofs 28 vcc 5v 12v 46 dvd to cpu vin ibias 29 r ntc 100k r ntc 100k v064 imon imona 15 17 16 4 isen2n isen2p 3 isen1p isen1n 6 5 fb 12 comp 13 pwm2 pwm1 50 51 v i n vcc pwm boot ugate phase lgate 12v pgnd rt9624a load v vdd_sense v ss_sense 34 isena2n isena2p 33 isena1p isena1n 36 35 rgnd 14 fba 31 compa 30 pwma2 pwma1 42 41 v i n vcc pwm boot ugate phase lgate 1 2 v pgnd rt9624a load v v d d n b _ s e n s e v ss_sense v v d d n b v v d d chip enable en 37 vsena pwm4 isen4p isen4n isen3n i s e n 3 p p w m 3 vsen 32 11 52 7 8 9 10 1 v in gnd 53 (exposed pad) r imon 2.34k r imona 2.84k r ibias 100k r ton 150k r tonnb 147k r s e n s e 3 5 6 0 svc 20 svd 21 svt 22 en 5v en 5v v cc5 v cc5 v cc5 v cc5 v cc5 15.82k 13.739k 10.94k 11.5k 0.47f 27pf 82pf 50.65k 10k 100 100 1f 2.2 0 0.1f 270f 1 3.3nf 0 510 1f v i n vcc pwm boot ugate phase lgate 12v pgnd rt9624a en 5v 1f 2.2 0 0.1f 270f 1 3.3nf 0 510 1f v i n vcc pwm boot ugate phase lgate 12v pgnd rt9624a en 5v 1f 2.2 0 0.1f 270f 1 3.3nf 0 510 1f r s e n s e 2 5 6 0 r s e n s e 1 5 6 0 820f x 8 1f 2.2 0 0.1f 0 270f 1 3.3nf 510 1f r s e n s e 4 5 6 0 v i n vcc pwm boot ugate phase lgate 1 2 v pgnd rt9624a en 5v 1f 2.2 0 0.1f 0 270f 1 3.3nf 510 1f r s e n s e a 2 5 6 0 v i n vcc pwm boot ugate phase lgate 1 2 v pgnd rt9624a en 5v 1f 2.2 0 0.1f 0 270f 1 3.3nf 510 1f r s e n s e a 1 5 6 0 100 100 820f x 3 82pf 39pf 10k 32.32k 0.1f 1 1 0.1f 0.1f 6.32k 0.1f 6.32k 1.27k 43.2k 470 0 1k 124k 20k 20k 1k 124k 0.1f 2.2 300k 510k 0.36 h / 0.72m 0.36 h / 0.72m 0.36 h / 0.72m 0.36 h / 0.72m 0.36 h / 0.72m 0.36 h / 0.72m 39 38 pgood pgooda 3.3v 10k 10k pwrok 19 ocp_l 27 vddio 18 vddio 1f 2.2 4.7k 4.7k 0.1f
RT8877C 18 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics vid = 1.1v time (20 s/div) core vr ovp and nvp v vdd (500mv/div) pgood (5v/div) ugate1 (50v/div) lgate1 (20v/div) vid = 1.1v time (10 s/div) core vr uvp v vdd (500mv/div) pgood (5v/div) ugate1 (50v/div) lgate1 (20v/div) boot vid = 0.8v time (200 s/div) core vr power on from en en (5v/div) pgood (5v/div) ugate1 (20v/div) v vdd (500mv/div) boot vid = 0.8v time (200 s/div) core vr power off from en en (5v/div) pgood (5v/div) ugate1 (20v/div) v vdd (500mv/div) i load = 80a to 160a time (4ms/div) core vr ocp_tdc ocp_l (2v/div) pgood (5v/div) i load (200a/div) ugate1 (20v/div) i load = 50a to 200a time (8 s/div) core vr ocp_spike ocp_l (2v/div) pgood (5v/div) i load (250a/div) ugate1 (20v/div)
RT8877C 19 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid = 1v to 1.4v, i load = 55a time (20 s/div) core vr dynamic vid up v vdd (500mv/div) i load (55a/div) svd (2v/div) svt (2v/div) vid = 1v to 1.1v, i load = 55a time (20 s/div) core vr dynamic vid up v vdd (500mv/div) i load (55a/div) svd (2v/div) svt (2v/div) vid = 0.4v to 1v, i load = 11a time (20 s/div) core vr dynamic vid up v vdd (500mv/div) i load (22a/div) svd (2v/div) svt (2v/div) vid = 1v to 1.06875v, i load = 55a time (20 s/div) core vr dynamic vid up v vdd (500mv/div) i load (55a/div) svd (2v/div) svt (2v/div) f load = 10khz, i load = 55a to 150a time (4 s/div) core vr load transient v vdd (100mv/div) i load (120a/div) vid = 1v to 1.2v, i load = 55a time (20 s/div) core vr dynamic vid up v vdd (500mv/div) i load (55a/div) svd (2v/div) svt (2v/div)
RT8877C 20 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (8 s/div) nb vr ocp_spike i load = 20a to 80a ocp_l (2v/div) pgooda (5v/div) i load (100a/div) ugatea1 (20v/div) time (200 s/div) nb vr power off from en boot vid = 0.8v en (5v/div) pgooda (5v/div) ugatea1 (20v/div) v vddnb (500mv/div) time (4ms/div) nb vr ocp_tdc i load = 30a to 60a ocp_l (2v/div) pgooda (5v/div) i load (100a/div) ugatea1 (20v/div) time (200 s/div) nb vr power on from en boot vid = 0.8v en (5v/div) pgooda (5v/div) ugatea1 (20v/div) v vddnb (500mv/div) time (4 s/div) core vr load transient f load = 10khz, i load = 150a to 55a v vdd (100mv/div) i load (120a/div) vid = 1.1v time (20 s/div) nb vr ovp and nvp v vddnb (500mv/div) pgooda (5v/div) ugatea1 (50v/div) lgatea1 (20v/div)
RT8877C 21 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (10 s/div) nb vr uvp vid = 1.1v v vddnb (500mv/div) pgooda (5v/div) ugatea1 (50v/div) lgatea1 (20v/div) vid = 0.4v to 1v, i load = 4.1a time (20 s/div) nb vr dynamic vid up svd (2v/div) svt (2v/div) v vddnb (500mv/div) i load (9a/div) vid = 1v to 1.4v, i load = 20.5a time (20 s/div) nb vr dynamic vid up svd (2v/div) svt (2v/div) v vddnb (500mv/div) i load (21a/div) vid = 1v to 1.2v, i load = 20.5a time (20 s/div) nb vr dynamic vid up svd (2v/div) svt (2v/div) v vddnb (500mv/div) i load (21a/div) vid = 1v to 1.06875v, i load = 20.5a time (20 s/div) nb vr dynamic vid up svd (2v/div) svt (2v/div) v vddnb (500mv/div) i load (21a/div) vid = 1v to 1.1v, i load = 20.5a time (20 s/div) nb vr dynamic vid up svd (2v/div) svt (2v/div) v vddnb (500mv/div) i load (21a/div)
RT8877C 22 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. f load = 10khz, i load = 20a to 60a time (4 s/div) nb vr load transient v vddnb (100mv/div) i load (45a/div) time (4 s/div) nb vr load transient f load = 10khz, i load = 60a to 20a v vddnb (100mv/div) i load (45a/div)
RT8877C 23 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information power ready (por) detection during start-up, the RT8877C will detect the voltage at the voltage input pins : vcc, en and dvd. when v cc > 4.2v and v dvd > 2.2v, the ic will recognize the power state of system to be ready (por = high) and wait for enable command at the en pin. after por = high and v en >2v, the ic will enter start-up sequence for both vdd rail and vddnb rail. if the voltage at any voltage input pin drops below low threshold (por = low), the ic will enter power down sequence and all the functions will be disabled. normally, connecting system power to the en pin and power stage vin (12v, through a voltage divider) to the dvd pin is recommended. the svid will be ready in 2ms (max) after the chip has been enabled. all the protection latches (ovp, ocp, uvp) will be cleared only after por = low. the condition of v en = low will not clear these latches. while vdd and vddnb regulate, dvd falls lower than 1.5v. then ic will shut down immediately until por recycle. figure 1. power ready (por) detection precise reference current generation the RT8877C includes complicated analog circuits inside the controller. the ic needs very precise reference voltage/ current to drive these analog circuits. the ic will auto generate a 2v voltage source at ibias pin, and a 100k resistor is required to be connected between ibias and analog ground, as shown in figure 2. through this connection, the ic will generate a 20 a current from the ibias pin to analog ground, and this 20 a current will be mirrored for internal use. note that other type of connection or other values of resistance applied at the ibias pin may cause functional failure, such as slew rate control, ofs figure 2. ibias setting boot vid when en goes high, both vdd and vddnb output begin to soft-start to the boot vid in ccm. table 6 shows the boot vid setting. the boot vid is determined by the svc and svd input states at en rising edge and it is stored in the internal register. the digital soft-start circuit ramps up the reference voltage at a controlled slew rate to reduce inrush current during start up. when all the output voltages are above power good threshold (300mv below boot vid) at the end of soft-start, the controller asserts power good after a time delay. initial startup vid (boot vid) svc svd vdd/vddnb output voltage (v) 0 0 1.1 0 1 1.0 1 0 0.9 1 1 0.8 table 6. 2-bit boot vid code start-up sequence after en goes high, the RT8877C starts up and operates according to the initial settings. figure 3 shows the simplified sequence timing diagram. the detailed operation is described in the following. accuracy, etc. in other words, the ibias pin can only be connected with a 100k resistor to gnd. the resistance accuracy of this resistor is recommended to be 1% or higher. + - ibias 100k current mirror + - 2v dvd + - + - por chip en 4.2v 2.2v 2v vcc en cmp cmp cmp + -
RT8877C 24 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. description of figure 3 : t0 : the RT8877C waits for vcc por. t1 : the svc pin and svd pin set the boot vid. boot vid is latched at en rising edge. svt is driven high by the RT8877C. t2 : the enable signal goes high and all output voltages ramp up to the boot vid in ccm. the soft-start slew rate is 3mv/ s. t3 : all output voltages are within the regulation limits and the pgood and pgooda signal goes high. t4 : the pwrok pin goes high and the svi2 interface starts running. the RT8877C waits for svid command from processor. t5 : a valid svid command transaction occurs between the processor and the RT8877C. t6 : the RT8877C starts votf (vid-on-the-fly) transition according to the received svid command and send a votf complete if the vid reaches target vid. figure 3. simplified sequence timing diagram t7 : the pwrok pin goes low and the svi2 interface stops running. all output voltages go back to the boot vid in ccm. t8 : the pwrok pin goes high again and the svi2 interface starts running. the RT8877C waits for svid command from processor. t9 : a valid svid command transaction occurs between the processor and the RT8877C. t10 : the RT8877C starts vid-on-the-fly transition according to the received svid command and send a votf complete if the vid reaches target vid. t11 : the enable signal goes low and all output voltages enter soft-shutdown mode. vcc svc svd en pwrok v vdd / v vddnb pgood/ pgooda boot vid svid boot vid vid vid t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t0 ccm ccm ccm ccm ccm ccm ccm send byte svid send byte svt votf complete votf complete
RT8877C 25 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power down sequence if the voltage at en pin falls below the enable falling threshold, the controller is disabled. the voltage at the pgood and pgooda pin will immediately go low at the loss of enable signal at the en pin and the controller executes soft-shutdown operation. the internal digital circuit ramps down the reference voltage at the same slew rate as that of in soft-start, making vdd and vddnb output voltages gradually decrease in ccm. each of the controller channels stops switching when the voltage at the voltage sense pin v sen /v sena , cross about 0.2v. the boot vid information stored in the internal register is cleared at por. this event forces the RT8877C to check the svc and svd inputs for a new boot vid when the en voltage goes high again. pgood and pgooda the pgood and pgooda are open-drain logic outputs. the 2 pins provide the power good signal when vdd and vddnb output voltage are within the regulation limits and no protection is triggered. these pins are typically tied to 3.3v or 5v power source through a pull-high resistor. during shutdown state (en = low) and the soft-start period, the pgood and pgooda voltages are pulled low. after a successful soft-start and vdd and vddnb output voltages are within the regulation limits, the pgood and pgooda are released high individually. the voltages at the pgood pin and pgooda pin are pulled low individually during normal operation when any of the following events occurs: over voltage protection, under voltage protection, over current protection, and logic low en voltage. if one rail triggers protection, another rail's pgood will be pull low after 5 s delay. svi2 wire protocol the RT8877C complies with amd's voltage regulator specification, which defines the serial vid interface 2 (svi2) protocol. with svi2 protocol, the processor directly controls the reference voltage level of each individual controller channel and determines which controller operates in power saving mode. the svi2 interface is a three wire bus that connects a single master to one or above slaves. the master initiates and terminates svi2 transactions and drives the clock, svc, and the data, svd, during a transaction. the slave drives the telemetry, svt during a transaction. the amd processor is always the master. the voltage regulator controller (RT8877C) is always the slave. the RT8877C receives the svid code and acts accordingly. the svi protocol supports 20mhz high speed mode i 2 c, which is based on svd data packet. table 7 shows the svd data packet. a svd packet consists of a ? start ? signal, three data bytes after each byte, and a ? stop ? signal. the 8-bit serial vid codes are listed in table1. after the RT8877C has received the stop sequence, it decodes the received serial vid code and executes the command. the controller has the ability to sample and report voltage and current for the vdd and vddnb domains. the controller reports this telemetry serially over the svt wire which is clocked by the processor driven svc. a bit tfn at svd packet along with the vdd and vddnb domain selector bits are used by the processor to change the telemetry functionality. the telemetry bit definition is listed in figure 4. the detailed svi2 specification is outlined in the amd voltage regulator and voltage regulator module (vrm) and serial vid interface 2.0 (svi2) specification. table 7. svd data packet bit time description 1 : 5 always 11000b 6 vdd domain selector bit, if set then the following two data bytes contain the vid for vdd, the psi state for vdd, and the load line slope trim and offset trim state for vdd. 7 vddnb domain selector bit, if set then the following two data bytes contain the vid for vddnb, the psi state for vddnb, and the load line sl ope trim and offset trim state for v ddnb. 8 always 0b 10 psi0_l 11 : 17 vid code bits [7:1] 19 vid code bit [0]
RT8877C 26 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. bit time description 20 psi1_l 21 tfn (telemetry functionality) 22 : 24 load line slope trim [2:0] 25 : 26 offset trim [1:0] figure 4. telemetry bit definition pwrok and svi2 operation the pwrok pin is an input pin, which is connected to the global power good signal from the platform. logic high at this pin enables the svi2 interface, allowing data transaction between processor and the RT8877C. once the RT8877C receives a valid svid code, it decodes the information from processor to determine which output plane is going to move to the target vid. the internal dac then steps the reference voltage in a controlled slew rate, making the output voltage shift to the required new vid. depending on the svid code, more than one controller channels can be targeted simultaneously in the vid transition. for example, vdd and vddnb voltages can ramp up/down at the same time. if the pwrok input goes low during normal operation, the svi2 protocol stops running. the RT8877C immediately drives svt high and modifies all output voltages back to the boot vid, which is stored in the internal register right after the controller is enabled. the controller does not read svd and svc inputs after the loss of pwrok. if the pwrok input goes high again, the svi2 protocol resumes running. the RT8877C then waits to decode the svid command from processor for a new vid and acts as previously described. the svi2 protocol is only running when the pwrok input goes high after the voltage at the en pin goes high; otherwise, the RT8877C will not soft-start due to incorrect signal sequence. vid-on-the-fly transition after the RT8877C has received a valid svid code, it enters ccm mode and executes the vid-on-the-fly transition by stepping up/down the reference voltage of the required controller channel(s) in a controlled slew rate, hence allowing the output voltage(s) to ramp up/down to the target vid. the output voltage slew rate during the vid-on-the- fly transition is faster than that in a soft-start/soft-shutdown operation. if the new vid level is higher than the current vid level, the controller begins stepping up the reference voltage with a typical slew rate of 12.5mv/ s upward to the target vid level. if the new level is lower than the current vid level, the controller begins stepping down the reference voltage with a typical slew rate of ? 12.5mv/ s downward to the target vid level. during the vid-on-the-fly transition, the RT8877C will force the controller channel to operate in ccm mode. if the controller channel operates in the power-saving mode prior to the vid-on-the-fly transition, it will be in ccm mode during the transition and then back to the power saving mode at the end of the transition. the voltage at the pgood pin and pgooda pin will keep high during the vid-on-the-fly transition. the RT8877C checks the output voltage for voltage-related protections and send a votf complete at the end of vid-on-the-fly transition. in the event of receiving a vid off code, the RT8877C steps the reference voltage of required controller channel down to zero, hence making the required output voltage decrease to zero. the voltage at the pgood pin and pgooda pin will remain high since the vid code is valid. svc svt stop start 1 2 3 4 5 6 7 11 12 13 14 15 16 10 17 vddnb voltage bit in voltage only mode; current bit in voltage and current mode 8 9 18 19 20 vdd voltage bits voltage and current mode selection bit time
RT8877C 27 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation mode transition the RT8877C supports operation mode transition function in vdd and vddnb controller for the psi[x]_l and command from amd processor. referring to table 7, the psi[x]_l bit in the svi2 protocol controls the operating mode of the RT8877C controller channels. the default operation mode of vdd and vddnb controller is ccm. when the vdd controller is in full-phase configuration and receives psi0_l = 0 and psi1_l = 1, the vdd controller will keep full-phase operation. when the vdd controller receives psi0_l = 0 and psi1_l = 0, the vdd controller takes phase shedding operation and enters diode emulation mode. in reverse, the vdd controller goes back to full-phase operation in ccm upon receiving psi0_l = 1 and psi1_l = 0 or 1, or psi0_l = 0 and psi1_l = 1. when the vddnb controller receives psi0_l = 0 and psi1_l = 1, it enters single-phase ccm, when the vddnb controller receives psi0_l = 0 and psi1_l = 0, it enters single-phase diode emulation mode. when the vddnb controller goes back to full-phase ccm operation after receiving psi0_l = 1 and psi1_l = 0 or 1. differential remote sense setting the vdd and vddnb controllers have differential, remote- sense inputs to eliminate the effects of voltage drops along the pc board traces, processor internal power routes and socket contacts. the processor contains on-die sense pins, vdd_sense, vddnb_sense and vss_sense. connect rgnd to vss_sense. for vdd controller, connect fb to vdd_sense with a resistor to build the negative input path of the error amplifier. connect fb_nb to vddnb_sense with a resistor using the same way in vdd controller. connect vss_sense to rgnd using separate trace as shown in figure 5. the precision reference voltages refer to rgnd for accurate remote sensing. figure 5. differential remote voltage sense connection vss_sense vddnb_sense vdd_sense rgnd rgnd_nb fb_nb fb vdd nb controller vdd controller processor set1 and set2 pin setting the RT8877C provides set1 pin for platform users to set the vdd and vddnb controller ocp_tdc threshold and internal ramp amplitude (rset & rseta), set2 pin to set vdd and vddnb controller ocp trigger delay (ocptrgdelay) and quick response threshold (qrth & qrtha). to set these pin, platform designers should use resistive voltage divider on these pins, refer to figure 6 and figure 7. the voltage at set1 and set2 pin is (1) = + ocptdc,d set1 ocptdc,u ocptdc,d r vvcc rr (2) = + qrth,d set2 qrth,u qrth,d r vvcc rr the adc monitors and decodes the voltage at this pin only once after power up. after adc decoding (only once), a 40 a current (when vcc = 5v) will be generated at the set1 and set2 pin for internal use. that is the voltage at set1 and set2 pin is (3) (4) ocptdc,u ocptdc,d set1 ocptdc,u ocptdc,d rr v40a rr =? + qrth,u qrth,d set2 qrth,u qrth,d rr v40a rr =? + from equation (1) to equation (4) and table 2 to table 5, platform users can set the ocp_tdc threshold, ocp trigger delay, internal ramp amplitude and quick response threshold for vdd and vddnb controller. figure 6. ocp_tdc/rset setting set1 vcc r ocptdc,u r ocptdc,d 40a (vcc = 5v) v ocptdc register adc 2.24v v ocptdc,div v ocptdc,div ocptdc = v ocptdc,div v ocptdc,2 RT8877C rset = v ocptdc,div
RT8877C 28 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 7. qrth/ocptrgdelay setting vdd controller active phase determination : before por the number of active phases is determined by the internal circuitry that monitors the isenxn voltages during start- up. normally, the vdd controller operates as a 4-phase pwm controller. pulling isen4n to vcc programs a 3- phase operation, pulling isen3n to vcc programs a 2- phase operation, and pulling isen2n to vcc programs a 1-phase operation. at en rising edge, vdd controller detects whether the voltages of isen2n, isen3n and isen4n are higher than ? vcc ? 0.5v ? respectively to decide how many phases should be active. phase selection is only active during por. when por = high, the number of active phases is determined and latched. the unused isenxp pins are recommended to be connected to vcc and unused pwm pins can be left floating. loop control the vdd controller adopts richtek's proprietary g-navp tm topology. g-navp tm is based on the finite gain peak current mode with ccrcot (constant current ripple constant on-time) topology. the output voltage, v vdd will decrease with increasing output load current. the control loop consists of pwm modulators with power stages, current sense amplifiers and an error amplifier as shown in figure 8. similar to the peak current mode control with finite compensator gain, the hs_fet on-time is determined by ccrcot on-time generator. when load current increases, v cs increases, the steady state comp voltage also increases and induces v vdd to decrease, thus achieving avp. a near-dc offset canceling is added to the output of ea to eliminate the inherent output offset of finite gain peak current mode controller. set2 vcc r qrth,u r qrth,d v qrth register adc 2.24v v qrth,div v qrth,div qrth = v qrth,div v qrth,2 RT8877C ocptrgdelay = v qrth,div 40a (vcc = 5v) figure 8. vdd controller : simplified schematic for droop and remote sense in ccm droop setting it's very easy to achieve active voltage positioning (avp) by properly setting the error amplifier gain due to the native droop characteristics as shown in figure 9. this target is to have v vdd = v dac, vdd ? i load x r droop (5) then solving the switching condition v comp2 = v cs in figure 8 yields the desired error amplifier gain as (6) (7) == i v droop g r2 a r1 r = sense i imon csx r 4 gr r10 where g i is the internal current sense amplifier gain. r sense is the current sense resistor. if no external sense resistor present, it is the equivalent resistance of the inductor. r droop is the equivalent load line resistance as well as the desired static output impedance. v vdd v vdd_sense pwmx + - isenxp isenxn x1 + - cmp v cs comp2 - + v in fb rgnd comp hs_fet ls_fet r x c x r c c c2 c1 r2 r1 ea - + v ss_sense v dac,vdd driver ccrcot pwm logic offset canceling r csx 0.4 imon vref r imon l r sense figure 9. vdd controller : error amplifier gain (a v ) influence on v vdd accuracy a v1 a v2 a v2 > a v1 v vdd load current 0
RT8877C 29 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. loop compensation optimized compensation of the vdd controller allows for best possible load step response of the regulator's output. a type-i compensator with one pole and one zero is adequate for proper compensation. figure 10 shows the compensation circuit. previous design procedure shows how to select the resistive feedback components for the error amplifier gain. next, c1 and c2 must be calculated for compensation. the target is to achieve constant resistive output impedance over the widest possible frequency range. the pole frequency of the compensator must be set to compensate the output capacitor esr zero : (8) = p c 1 f 2cr = c c x r c2 r2 (9) (10) = sw 1 c1 r1 f where c is the capacitance of output capacitor, and r c is the esr of output capacitor. c2 can be calculated as follows : the zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. such that, figure 10. vdd controller : compensation circuit ton setting high frequency operation optimizes the application for the smaller component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low frequency operation offers the best overall efficiency at the expense of component size and board space. figure 11 shows the on-time setting circuit. connect a resistor (r ton ) between v in and tonset to set the on-time of ugate : (11) ? <= ? 12 ton on dac in dac 24.4 10 r t (0.5vv 1.8v) vv (12) ? = ? 12 ton dac on dac in dac 13.55 10 r v t (v 1.8v) vv (13) s(max) on hs delay dac(max) load(max) on _ ls fet l droop in(max) load(max) on _ ls fet on _ hs fet 1 f(khz) x tt vi x r dcrr vi x r r ? ? ?? = ? ?? ++? ?? ?? +? ?? where t on is the ugate turn on period, v in is input voltage of the vdd controller, and v dac is the dac voltage. when v dac is larger than 1.8v, the equivalent switching frequency may be over 500khz, and this too fast switching frequency is unacceptable. therefore, the vdd controller implements a pseudo constant frequency technology to avoid this disadvantage of ccrcot topology. when v dac is larger than 1.8v, the on-time equation will be modified to : on-time translates only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in external hs-fet. also, the dead-time effect increases the effective on-time, which in turn reduces the switching frequency. it occurs only in ccm and during dynamic output voltage transitions. when the inductor current reverses at light or negative load currents, with reversed inductor current, the phase goes high earlier than normal, extending the on-time by a period equal to the hs-fet rising dead time. for better efficiency of the given load range, the maximum switching frequency is suggested to be : where f s(max) is the maximum switching frequency, t hs- delay is the turn-on delay of hs-fet, v dac(max) is the maximum v dac of application, v in(max) is the maximum application input voltage, i load(max) is the maximum load of application, r on_ls-fet is the low side fet r ds(on) , r on_hs-fet is the high side fet r ds(on) , dcr l is the equivalent resistance of the inductor, and r droop is the load line setting. figure 11. vdd controller : on-time setting with r c filter v vdd_sense - + v ss_sense fb rgnd comp c2 c1 r2 ea r1 - + vdac ccrcot on-time computer tonset r ton r1 c1 v in vdac on-time
RT8877C 30 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. current sense setting the current sense topology of the vdd controller is continuous inductor current sensing. therefore, the controller has less noise sensitive. low offset amplifiers are used for current balance, loop control and over current detection. the isenxp and isenxn pins denote the positive and negative input of the current sense amplifier of each phase. users can either use a current sense resistor or the inductor's dcr l for current sensing. using the inductor's dcr l allows higher efficiency as shown in figure 12. figure 12. vdd controller : lossless inductor sensing in order to optimize transient performance, r x and c x must be set according to the equation below : (14) x x l l rc dcr = (15) then the proportion between the phase current, i l , and the sensed current, i senxn , is driven by the value of the effective sense resistance, r csx , and the dcr l of the inductor. the resistance value of r csx is limited by the internal circuitry. the recommended value is from 500 to 1.2k . considering the inductance tolerance, the resistor r x has to be tuned on board by examining the transient voltage. if the output voltage transient has an initial dip below the minimum load line requirement and the recovery is too fast causing a ring back. vice versa, with a resistance too large the output voltage transient has only a small initial dip with a slow recovery. using current sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. considering the equivalent inductance (l esl ) of the current sense resistor, an rc filter is recommended. the rc filter calculation method is similar to the above mentioned inductor equivalent resistance sensing method. per-phase over current protection the vdd controller provides over current protection in each phase. for vdd controller in four-phase configuration, either phase can trigger per-phase over current protection (phocp). the vdd controller senses each phase inductor current i l , and phocp comparator compares sensed current with phocp threshold current, as shown in figure 13. figure 13. vdd controller : per-phase ocp setting the controller will turn off all high side/low side mosfets to protect cpu if the per-phase over current protection is triggered. current balance the vdd controller implements internal current balance mechanism in the current loop. the vdd controller senses and compares per-phase current signal with average current. if the sensed current of any particular phase is larger than average current, the on-time of this phase will be adjusted to be shorter. initial offset and external offset (over clocking offset function) the vdd controller features over clocking offset function which provides the possibility of wide range off set of output voltage. the initial offset function can be implemented through the svi interface. when the ofs pin voltage < 0.3v at en rising edge, the initial offset is disabled. the external offset function can be implemented by set2 pin setting. for example, referring to table 8, when the both rail external offset functions are enabled, the output voltage is : isenxp isenxn l dcr l r x c x v vdd + - r csx i l i senxn (16) (17) l l,perphase(max) csx dcr 1 i = 10a r8 l,perphase(max) l csx idcr r 810a = the resistor r csx determines phocp threshold. current mirror 10a phocp trigger i senaxn senaxn 1 i 8 l senxn l csx dcr ii r =
RT8877C 31 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dynamic vid enhancement during a dynamic vid event, the charging (dynamic vid up) or discharging (dynamic vid down) current causes unwanted load-line effect which degrades the settling time performance. the RT8877C will hold the inductor current to hold the load-line during a dynamic vid event. the vdd controller will always enter four-phase configuration when vdd controller receives dynamic vid up and vdd controller will hold the operating state when vdd controller receives dynamic vid down. ramp amplitude adjust when the vdd controller takes phase shedding operation and enters diode emulation mode, the internal ramp of vdd controller will be modified for the reason of stability. in case of smooth transition into dem, the ccm ramp amplitude should be designed properly. the RT8877C provides set1 pin for platform users to set the ramp amplitude of the vdd controller in ccm. where i l is the phase current, r csx is the effective sense resistance, and r imon is the current monitor current setting resistor. note that the imon pin cannot be monitored. the adc circuit of the vdd controller monitors the voltage variation at the imon pin from 0v to 3.19375v, and this voltage is decoded into digital format and stored into output_current register. the adc divides 3.19375v into 511 levels, so lsb = 3.19375v / 511 = 6.25mv. quick response the vdd controller utilizes a quick response feature to support heavy load current demand during instantaneous load transient. the vdd controller monitors the current of the v vdd_sense , and this current is mirrored to internal quick response circuit. at steady state, this mirrored current will not trigger a quick response. when the v vdd_sense voltage drops abruptly due to load apply transient, the mirrored current flowing into quick response circuit will also increase instantaneously. the qr threshold setting for vdd controller refers to table 4. figure 14. vdd controller : quick response triggering circuit when quick response is triggered, the quick response circuit will generate a quick response pulse. the pulse width of quick response is almost the same with t on . (18) (19) =? vdd dac load droop external _ ofs initial _ ofs vv i x r + v + v ? external _ ofs ofs v = v1.2v v initial_ofs is the initial offset voltage set by svi interface, and the external offset voltage, v external_ofs is set by supplying a voltage into ofs pin. it can be calculated as below : if supplying 1.3v at ofs pin , it will achieve 100mv offset at the output. connecting a filter capacitor between the ofs pin and gnd is necessary. designers can design the offset slew rate by properly setting the filter bandwidth. core_ offset_ en nb_ offset_ en description 0 0 disable external offset function. 0 1 nb rail external offset is set by ofs pin voltage. 1 0 core rail external offset is set by ofsa pin voltage. 1 1 core rail external offset is set by ofs pin voltage, and nb rail external offset is set by ofsa pin voltage. table 8. external offset function setting for vdd and vddnb controller current monitoring and current reporting the vdd controller provides current monitoring function via inductor current sensing. in g-navp tm technology, the output voltage is dependent on output current, and the current monitoring function is achieved by this characteristic of output voltage. the equivalent output current will be sensed from inductor current sensing and mirrored to imon pin. the resistor connected to imon pin determines voltage of the imon output. (20) l imon l,sum imon csx dcr v = i r 0.64 r + + - cmp qr pulse generation circuit v vdd_sense - + qrth
RT8877C 32 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. and set the ocp-tdc threshold, i l(tdc) , refer to some percentage of ocp-spike through table 2. over voltage protection (ovp) the over voltage protection circuit of the vdd controller monitors the output voltage via the v sen pin after por. when vid is lower than 0.9v, once v sen exceeds ? 0.9v + 325mv ? , ovp is triggered and latched. when vid is larger than 0.9v, once v sen exceeds the internal reference by 325mv, ovp is triggered and latched. the vdd controller will try to turn on low side mosfets and turn off high side mosfets of all active phases of the vdd controller to protect the cpu. when ovp is triggered by one rail, the other rail will also enter soft shut down sequence. a 1 s delay is used in ovp detection circuit to prevent false trigger. after generating a quick response pulse, the pulse is then applied to the on-time generating circuit, and all the active phases' on-time will be overridden by the quick response pulse. over current protection the RT8877C has dual ocp mechanism. the dual ocp mechanism has two types of thresholds. the first type, referred to as ocp-tdc, is a time and current based threshold. ocp-tdc should trip when the average output current exceeds tdc by some percentage and for a period of time. this period of time is referred to as the trigger delay. the second type, referred to as ocp-spike, is a current based threshold. ocp-spike should trip when the cycle-by-cycle output current exceeds iddspike by some percentage. if either mechanism trips, then the vdd controller asserts ocp_l and delays any further action. this delay is called an action delay. refer to action delay time. after the action delay has expired and the vdd controller has allowed its current sense filter to settle out and the current has not decreased below the threshold, then the vdd controller will turn off both high side mosfets and low side mosfets of all channels. users can set ocp-spike threshold, i l,sum (spike) , by the current monitor resistor r imon of the following equation : negative voltage protection (nvp) during ovp latch state, the vdd controller also monitors the v sen pin for negative voltage protection. since the ovp latch continuously turns on all low side mosfets of the vdd controller, the vdd controller may suffer negative output voltage. as a consequence, when the v sen voltage drops below 0v after triggering ovp, the vdd controller will trigger nvp to turn off all low side mosfets of the vdd controller while the high side mosfets remains off. after triggering nvp, if the output voltage rises above 0v, the ovp latch will restart to turn on all low side mosfets. the nvp function will be active only after ovp is triggered. under voltage protection (uvp) the vdd controller implements under voltage protection of v out,vdd . if v sen is less than the internal reference by 325mv, the vdd controller will trigger uvp latch. the uvp latch will turn off both high side and low side mosfets. when uvp is triggered by one rail, the other rail will also enter soft shut down sequence. a 3 s delay is used in uvp detection circuit to prevent false trigger. under voltage lock out (uvlo) during normal operation, if the voltage at the vcc or dvd pin drops below por threshold, the vdd controller will trigger uvlo. the uvlo protection forces all high side mosfets and low side mosfets off by shutting down internal pwm logic drivers. a 3 s delay is used in uvlo detection circuit to prevent false trigger. vddnb controller vddnb controller disable the vddnb controller can be disabled by connecting isena1n to a voltage higher than vcc. if not in use, isenaxp is recommended to be connected to vcc, while pwmax is left floating. when vddnb controller is disabled, all svid commands related to vddnb controller will be rejected. loop control the vddnb controller adopts richtek's proprietary g- navp tm topology. g-navp tm is based on the finite gain peak current mode with ccrcot (constant current ripple (21) csx l,sum (spike) limon r 3.19375 0.64 i= dcr r ?
RT8877C 33 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 15. vddnb controller : simplified schematic for droop and remote sense in ccm droop setting it's very easy to achieve active voltage positioning (avp) by properly setting the error amplifier gain due to the native droop characteristics as shown in figure 16. this target is to have v vddnb = v dac,vddnb ? i load x r droop (22) then solving the switching condition v comp2 = v cs in figure 17 yields the desired error amplifier gain as (23) (24) == i v droop g r2 a r1 r = sense i imon csx r 8 where g r r10 where g i is the internal current sense amplifier gain. r sense is the current sense resistor. if no external sense resistor present, it is the equivalent resistance of the inductor. r droop is the equivalent load line resistance as well as the desired static output impedance. (26) (27) (25) = p c 1 f 2cr = c c x r c2 r2 = sw 1 c1 r1 f where c is the capacitance of output capacitor, and r c is the esr of output capacitor. c2 can be calculated as follows : the zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. such that, figure 17. vddnb controller : compensation circuit v vddnb_sense - + v ss_sense fba rgnd compa c2 c1 r2 ea r1 - + v dac,vddnb constant on-time) topology. the output voltage, v vddnb will decrease with increasing output load current. the control loop consists of pwm modulators with power stages, current sense amplifiers and an error amplifier as shown in figure 15. similar to the peak current mode control with finite compensator gain, the hs_fet on-time is determined by ccrcot on-time generator. when load current increases, v cs increases, the steady state compa voltage also increases and induces v vddnb to decrease, thus achieving avp. a near-dc offset canceling is added to the output of ea to eliminate the inherent output offset of finite gain peak current mode controller. a v1 a v2 a v2 > a v1 v vddnb load current 0 figure 16. vddnb controller : error amplifier gain (a v ) influence on v vddnb accuracy loop compensation optimized compensation of the vddnb controller allows for best possible load step response of the regulator?s output. a type-i compensator with one pole and one zero is adequate for proper compensation. figure 17 shows the compensation circuit. previous design procedure shows how to select the resistive feedback components for the error amplifier gain. next, c1 and c2 must be calculated for compensation. the target is to achieve constant resistive output impedance over the widest possible frequency range. the pole frequency of the compensator must be set to compensate the output capacitor esr zero : v vddnb v vddnb_sense pwmax + - isenaxp isenaxn x2 + - cmp v cs comp2 - + v in fba rgnd compa hs_fet ls_fet r x c x r c c c2 c1 r2 r1 ea - + v ss_sense v dac, vddnb driver ccrcot pwm logic offset canceling r csx 0.4 imona vref r imona l r sense
RT8877C 34 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? = ? on dac 12 ton dac,vddnb in dac,vddnb t (v 1.8v) 13.55 10 r v vv current sense setting the current sense topology of the vddnb controller is continuous inductor current sensing. therefore, the controller has less sensitive noise. low offset amplifiers are used for current balance, loop control and over current detection. the isenaxp and isenaxn pins denote the positive and negative input of the current sense amplifier of each phase. users can either use a current sense resistor or the inductor's dcr l for current sensing. using the inductor's dcr l allows higher efficiency as shown in figure 19. figure 19. vddnb controller : lossless inductor sensing in order to optimize transient performance, r x and c x must be set according to the equation below : (31) then the proportion between the phase current, i l , and the sensed current, i senaxn , is driven by the value of the effective sense resistance, r csx , and the dcr l of the (29) on-time translates only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in external hs-fet. also, the dead-time effect increases the effective on-time, which in turn reduces the switching frequency. it occurs only in ccm and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents, with reversed inductor current, the phase goes high earlier than normal, extending the on-time by a period equal to the hs-fet rising dead time. for better efficiency of the given load range, the maximum switching frequency is suggested to be : (30) s(max) on hs delay dac(max) load(max) on _ ls fet l droop in(max) load(max) on _ ls fet on _ hs fet 1 f(khz) x tt v i x r dcr r vi x r r ? ? ?? = ? ?? ++? ?? ?? +? ?? where f s(max) is the maximum switching frequency, t hs- delay is the turn-on delay of hs-fet, v dac(max) is the maximum v dac,vddnb of application, v in(max) is the maximum application input voltage, i load(max) is the maximum load of application, r on_ls-fet is the low side fet r ds(on) , r on_hs-fet is the high side fet r ds(on) , dcr l is the equivalent resistance of the inductor, and r droop is the load line setting. figure 18. vddnb controller : on-time setting with r c filter ccrcot on-time computer tonseta r ton r1 c1 v in v dac,vddnb on-time ton setting high frequency operation optimizes the application for the smaller component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low frequency operation offers the best overall efficiency at the expense of component size and board space. figure 18 shows the on-time setting circuit. connect a resistor (r ton ) between v in and tonseta to set the on-time of ugate : (28) ? <= ? 12 ton on dac in dac,vddnb 24.4 10 r t (0.5vv 1.8v) vv where t on is the ugate turn on period, v in is input voltage of the vddnb controller, and v dac,vddnb is the dac voltage. when v dac,vddnb is larger than 1.8v, the equivalent switching frequency may be over 500khz, and this too fast switching frequency is unacceptable. therefore, the vddnb controller implements a pseudo constant frequency technology to avoid this disadvantage of ccrcot topology. when v dac,vddnb is larger than 1.8v, the on-time equation will be modified to : x x l l rc dcr = isenaxp isenaxn l dcr l r x c x v vddnb + - r csx i l isenaxn
RT8877C 35 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 20. vddnb controller : per-phase ocp setting the controller will turn off all high side/low side mosfets to protect cpu if the per-phase over current protection is triggered. current mirror 10a phocp trigger i senaxn senaxn 1 i 8 if supplying 1.3v at ofsa pin, it will achieve 100mv offset at the output. connecting a filter capacitor between the ofsa pin and gnd is necessary. designers can design the offset slew rate by properly setting the filter bandwidth. dynamic vid enhancement during a dynamic vid event, the charging (dynamic vid up) or discharging (dynamic vid down) current causes unwanted load-line effect which degrades the settling time performance. the RT8877C will hold the inductor current to hold the load-line during a dynamic vid event. the vddnb controller will always enter two-phase configuration when vddnb controller receives dynamic vid up and vddnb controller will hold the operating state when vddnb controller receives dynamic vid down. ramp amplitude adjust when the vddnb controller takes phase shedding operation and enters diode emulation mode, the internal ramp of vddnb controller will be modified for the reason of stability. in case of smooth transition into dem, the ccm ramp amplitude should be designed properly. the RT8877C provides set1 pin for platform users to set the ramp amplitude of the vddnb controller in ccm. (32) considering the inductance tolerance, the resistor r x has to be tuned on board by examining the transient voltage. if the output voltage transient has an initial dip below the minimum load line requirement and the recovery is too fast causing a ring back. vice versa, with a resistance too large the output voltage transient has only a small initial dip with a slow recovery. using current sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. considering the equivalent inductance (l esl ) of the current sense resistor, an rc filter is recommended. the rc filter calculation method is similar to the above mentioned inductor equivalent resistance sensing method. per-phase over current protection the vddnb controller provides over current protection in each phase. for vddnb controller in two-phase configuration, either phase can trigger per-phase over current protection (phocp). the vddnb controller senses each phase inductor current i l , and phocp comparator compares sensed current with phocp threshold current, as shown in figure 20. inductor. the resistance value of r csx is limited by the internal circuitry. the recommended value is from 500 to 1.2k . l senaxn l csx dcr ii r = (36) (35) initial offset and external offset (over clocking offset function) the vddnb controller features over clocking offset function which provides the possibility of wide range offset of output voltage. the initial offset function can be implemented through the svi interface. when the ofsa pin voltage < 0.3v at en rising edge, the initial offset is disabled. the external offset function can be implemented by set2 pin setting. for example, referring to table 8, when the both rail external offset functions are enabled, the output voltage is : =? vddnb dac,vddnb load droop external _ ofsa initial _ ofsa vv ir + v + v ? external _ ofsa ofsa v = v1.2v v initial_ofsa is the initial offset voltage set by svi interface, and the external offset voltage, v external_ofsa is set by supplying a voltage into ofsa pin. it can be calculated as below : (33) (34) l l,perphase(max) csx dcr 1 i = 10a r8 l,perphase(max) l csx idcr r 810a = the resistor r csx determines phocp threshold.
RT8877C 36 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 21. vddnb controller : quick response triggering circuit when quick response is triggered, the quick response circuit will generate a quick response pulse. the pulse width of quick response is almost the same with t on . and set the ocp-tdca threshold, i l(tdca) , refer to some percentage of ocp-spikea through table 3. over voltage protection (ovp) the over voltage protection circuit of the vddnb controller monitors the output voltage via the v sena pin after por. when vid is lower than 0.9v, once v sena exceeds ? 0.9v + 325mv ? , ovp is triggered and latched. when vid is larger than 0.9v, once v sena exceeds the internal reference by 325mv, ovp is triggered and latched. the vddnb controller will try to turn on low side mosfets and turn off high side mosfets of all active phases of the vddnb controller to protect the cpu. when ovp is triggered by one rail, the other rail will also enter soft shut down sequence. a 1 s delay is used in ovp detection circuit to prevent false trigger. - + + - cmp qr pulse generation circuit v vddnb_sense qrtha (37) where i l is the phase current, r csx is the effective sense resistance, and r imona is the current monitor current setting resistor. note that the imona pin cannot be monitored. the adc circuit of the vddnb controller monitors the voltage variation at the imona pin from 0v to 3.19375v, and this voltage is decoded into digital format and stored into output_current register. the adc divides 3.19375v into 511 levels, so lsb = 3.19375v / 511 = 6.25mv. quick response the vddnb controller utilizes a quick response feature to support heavy load current demand during instantaneous load transient. the vddnb controller monitors the current of the v vddnb_sense , and this current is mirrored to internal quick response circuit. at steady state, this mirrored current will not trigger a quick response. when the v vddnb_sense voltage drops abruptly due to load apply transient, the mirrored current flowing into quick response circuit will also increase instantaneously. the qr threshold setting for vddnb controller refers to table 5. current monitoring and current reporting the vddnb controller provides current monitoring function via inductor current sensing. in g-navp tm technology, the output voltage is dependent on output current, and the current monitoring function is achieved by this characteristic of output voltage. the equivalent output current will be sensed from inductor current sensing and mirrored to imona pin. the resistor connected to imona pin determines voltage of the imona output. l imona l,sum imona csx dcr v = i 2 r 0.64 r + after generating a quick response pulse, the pulse is then applied to the on-time generation circuit, and all the active phases' on-times will be overridden by the quick response pulse. over current protection the RT8877C has dual ocp mechanism. the dual ocp mechanism has two types of thresholds. the first type, referred to as ocp-tdca, is a time and current based threshold. ocp-tdca should trip when the average output current exceeds tdca by some percentage and for a period of time. this period of time is referred to as the trigger delay. the second type, referred to as ocp- spikea, is a current based threshold. ocp-spikea should trip when the cycle-by-cycle output current exceeds iddspikea by some percentage. if either mechanism trips, then the vddnb controller asserts ocp_l and delays any further action. this delay is called an action delay. refer to action delay time. after the action delay has expired and the vddnb controller has allowed its current sense filter to settle out and the current has not decreased below the threshold, then the vddnb controller will turn off both high side mosfets and low side mosfets of all channels. users can set ocp-spikea threshold, i l,sum (spikea) , by the current monitor resistor r imona of the following equation : (38) csx l,sum (spikea) limona r 3.19375 0.64 i= 2dcr r ?
RT8877C 37 ds8877c-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. negative voltage protection (nvp) during ovp latch state, the vddnb controller also monitors the v sena pin for negative voltage protection. since the ovp latch continuously turns on all low side mosfets of the vddnb controller, the vddnb controller may suffer negative output voltage. as a consequence, when the v sena voltage drops below 0v after triggering ovp, the vddnb controller will trigger nvp to turn off all low side mosfets of the vddnb controller while the high side mosfets remains off. after triggering nvp, if the output voltage rises above 0v, the ovp latch will restart to turn on all low side mosfets. the nvp function will be active only after ovp is triggered. under voltage protection (uvp) the vddnb controller implements under voltage protection of v out,vddnb . if v sena is less than the internal reference by 325mv, the vddnb controller will trigger uvp latch. the uvp latch will turn off both high side and low side mosfets. when uvp is triggered by one rail, the other rail will also enter soft shut down sequence. a 3 s delay is used in uvp detection circuit to prevent false trigger. under voltage lock out (uvlo) during normal operation, if the voltage at the vcc or dvd pin drops below por threshold, the vddnb controller will trigger uvlo. the uvlo protection forces all high side mosfets and low side mosfets off by shutting down internal pwm logic drivers. a 3 s delay is used in uvlo detection circuit to prevent false trigger. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-52l 6x6 package, the thermal resistance, ja , is 26.5 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (26.5 c/w) = 3.77w for wqfn-52l 6x6 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 22 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 22. derating curve of maximum power dissipation 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0255075100125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8877C 38 ds8877c-00 november 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension w-type 52l qfn 6x6 package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 5.900 6.100 0.232 0.240 d2 4.650 4.750 0.183 0.187 e 5.900 6.100 0.232 0.240 e2 4.650 4.750 0.183 0.187 e 0.400 0.016 l 0.350 0.450 0.014 0.018

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